Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel.
One particular consideration in using strain engineering in CMOS technologies is that PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. Different approaches to strain engineering induce strain locally, allowing both n-channel and p-channel strain to be modulated independently.
NFET and PFET thus require opposite strain for mobility enhancement. Therefore a mobility enhancement for one of the transistors can lead to degradation of performance for the other transistor. To avoid degradation of performance for one of the transistor types, or to obtain mobility enhancement for both at the same time is not straightforward.
One known approach involves the use of a strain-inducing capping layer. CVD silicon nitride is a common choice for a strained capping layer, in that the magnitude and type of strain (e.g. tensile versus compressive) may be adjusted by modulating the deposition conditions, especially temperature. Standard lithography patterning techniques can be used to selectively deposit strain-inducing capping layers, to deposit a compressive film over only the PMOS, for example.
Another way to tackle this is by performing multiple epitaxial growth steps of different types of strained-relaxed buffers and channels. However, the epitaxial growth steps need to be masked such as the growth is performed either on the nFET or on the pFET. These masking steps are both technically challenging and costly.